pulp-platform

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

mempool

A 256-RISC-V-core system with low-latency access into shared L1 memory.

cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

FlooNoC

A Fast, Low-Overhead On-chip Network

iDMA

A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)

carfield

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

spatz

Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.

pulp_cluster

The multi-core cluster of a PULP system.

snitch_cluster

An energy-efficient RISC-V floating-point compute cluster.

pulp-runtime

Simple runtime for Pulp platforms

redmule

pulp-trainlib

Floating-Point Optimized On-Device Learning Library for the PULP Platform.

axi_llc

cheshire-ihp130-o

cva6

This is the fork of CVA6 intended for PULP development.

banshee

cvfpu

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

hci

Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores

neureka

2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters

gpio

Parametric GPIO Peripheral

pulp-nn-mixed

redundancy_cells

hwpe-ctrl

IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system

obi

regression_tests

astral

A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.

ELAU

pulp-ethernet

opentitan

OpenTitan: Open source silicon root of trust

cluster_icache