pranavanantharam / FIFO-Memory

FIFO Memory Implementation using Verilog

FIFO Memory Implementation using Xilinx Vivado

Prerequisites

• Xilinx Vivado 2018.x+

Instructions

1. Open both files using Xilinx Vivado.
2. Run FIFObuffer.v to generate digital design.
3. Run FIFObuffer_tb.v ( testbench file ) to generate results.
4. View results by running Simulation.