phatonix

Sourcetrail

Sourcetrail - free and open-source interactive source explorer

scala

Scala 2 compiler and standard library. Scala 2 bugs at https://github.com/scala/bug; Scala 3 at https://github.com/scala/scala3

lua

A copy of the Lua development repository, as seen by the Lua team. Mirrored irregularly. Please DO NOT send pull requests or any other stuff. All communication should be through the Lua mailing list https://www.lua.org/lua-l.html

XiangShan

Open-source high-performance RISC-V processor

scala-exercises

The easy way to learn Scala.

gnvim

GUI for neovim, without any web bloat

almond

A Scala kernel for Jupyter

gem5

The official repository for the gem5 computer-system architecture simulator.

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

openc910

OpenXuantie - OpenC910 Core

rsd

RSD: RISC-V Out-of-Order Superscalar Processor

awesome-hdl

Hardware Description Languages

firrtl

Flexible Intermediate Representation for RTL

gtkwave

GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

chisel-template

A template project for beginning new Chisel work

almalinux-deploy

EL to AlmaLinux migration tool.

pulp

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

sv-parser

SystemVerilog parser library fully compliant with IEEE 1800-2017

ctags-win32

Universal Ctags Win32 daily builds

SuperScalar-RISCV-CPU

SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.

qflow

Qflow full end-to-end digital synthesis flow for ASIC designs

svunit

Toooba

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT

treadle

Chisel/Firrtl execution engine

EpicSim

EpicSim Project

sveditor

SystemVerilog Development Environment

tbengy

Python Tool for UVM Testbench Generation

homebrew-verible

ieee1800_2017

SystemVerilog preprocessor, lexer and parser with examples

chisel-template