pengzhi1998 / Deep-Pipelined-CPU-on-FPGA

Eight-staged-pipelined-CPU

Pipelined CPU implemented on FPGA

CPU designed and implemented by Zhongyao Cao, Sufang Yang as well as Pengzhi Yang. All the parts were written in verilog.

This is the curriculum design for our computer achitecture course. We built our own 5 staged pipelined CPU and added deep pipeline in ALU to make its efficiency much higher. And we ran the FFT algorithm on it and implemented it on FPGA.