The implementation of some modules and basic projects of CAD in VHDL
- PEncoder: A 2^n-to-n Priority Encoder with 2^n bit as input and n bit as output.
- ParityBitGenerator: A Parity Bit Generator with 7 bit as input and 2 bit as output called Parity_odd and Parity_even.
- SevenSegDecoder: A 7 Segment Decoder with 4 bit as input and 7 bit as input based on a given truth table.
- TwosComplementProblem: A simple problem with n bit as input and n bit as output. If the number of '1's in input vector is greater than the half of vector length then output must be the two's complement of the input, else it must be the same as input.
- ALU: A 16 bit ALU with two 16 bit input (A, B), 3 bit command control input and 1 bit ALUEn.
- 11101 State Machine: A state machine that detects "11101" strings.
- (odd number of 1's)(at least two 0's)11 State Machine: A state machine that detects "(odd number of 1's)(at least two 0's)11" strings.
- Reserach: Search about difference between inertial, transport and reject.
- Computer-Aided Digital System Design
- Autumn 2018
- Dr. Mahdi Aminian [Web Page]
- University of Guilan [Website]