Introduction

This repository documents the steps I put together trying to get u-boot to boot on the Microblaze soft processor synthesized on an ARTY Z7-20 board. Available xilinx documentation seems outdated and doesn't help much.

Maybe the info presented here will be a decent starting point to anyone wanting to manually boot u-boot on Microblaze.

Overview

The design is based around the ARM fsbl. The fsbl programs the FPGA, loads the u-boot proper image to DDR, wakes the Microblaze processor from reset and then puts the ARM processor to sleep. U-boot SPL is bundled with the bitstream using updatemem and loaded into the Microblaze BRAM local memory.

Board design

This repository contains an archived example Vivado 2020.1 project (vivado/ directory) that you can adapt (change the board part and the UART Rx/Tx pins according to your board).

Tested config:

Memory map:

0x00000000 - 0x0001FFFF -> 128KB BRAM
0x04000000 - 0x07FFFFFF -> 64MB DRAM
0x40000000 - 0x4000FFFF -> AXI GPIO
0x41200000 - 0x4120FFFF -> AXI Interrupt Controller
0x41C00000 - 0x41C0FFFF -> AXI Timer
0x40600000 - 0x4060FFFF -> AXI UARTlite

Ethernet and flash support were not tested yet. For reference, vivado/bd directory contains some screenshots and the block design exported tcl script:

-- Full block design diagram --
-- Address editor --
Microblaze configs: 1 2 3 4 5 6

Build

Prepare build environment

Make sure Vivado and Vitis environments are sourced.

Clone repositories and download prebuilt little endian toolchain for Microblaze:

mkdir build && cd build
mkdir vivado_output
git clone https://github.com/Xilinx/device-tree-xlnx.git
git clone https://github.com/ovpanait/u-boot-microblaze-howto.git
git clone https://github.com/u-boot/u-boot.git
wget https://toolchains.bootlin.com/downloads/releases/toolchains/microblazeel/tarballs/microblazeel--glibc--bleeding-edge-2021.11-1.tar.bz2
tar -xvf microblazeel--glibc--bleeding-edge-2021.11-1.tar.bz2
export CROSS_COMPILE="$(realpath microblazeel--glibc--bleeding-edge-2021.11-1/bin)/microblazeel-linux-"

Generate bitstream and export mmi/xsa files

Generate bitstream for the block design described earlier (you can use the archived project directly and adjust the board part and Rx/Tx pin assignments in constraints file).

Run the following vivado tcl commands to generate the xsa/mmi files:

file copy -force [glob "[get_property DIRECTORY [current_project]]/[get_property NAME [current_project]].runs/impl_1/*.bit"] <path>/vivado_output/project.bit
write_hw_platform -fixed -force -file <path>/vivado_output/project.xsa
write_mem_info -force -file <path>/vivado_output/project.mmi

Generate dtb

XSA_FILE="$(realpath vivado_output/project.xsa)"
DTS_SDK="$(realpath device-tree-xlnx)"
mkdir dts
xsct <<EOF
hsi open_hw_design "${XSA_FILE}"
hsi set_repo_path "${DTS_SDK}"
hsi create_sw_design device-tree -os device_tree -proc microblaze_0
hsi generate_target -dir dts
EOF

The memory node for PS DDR, which is accesible by Microblaze, is not generated by the current tools. We add it manually instead. Also, in order for u-boot SPL to use the serial console, "u-boot,dm-spl;" fragments must be added to AXI Uartlite IP node.

cd dts

cat >> system-top.dts <<EOF
/ {
	memory {
		device_type = "memory";
		reg = <0x04000000 0x04000000>;
	};
};

&amba_pl {
 u-boot,dm-spl;
};

&axi_uartlite_0 {
 u-boot,dm-spl;
};
EOF
gcc -I my_dts -E -nostdinc -undef -D__DTS__ -x assembler-with-cpp -o system.dts system-top.dts
dtc -I dts -O dtb -o system.dtb system.dts
cd ..

Build u-boot

In this example we configure u-boot to boot from RAM (u-boot proper image is preloaded to DRAM by the ARM fsbl). A custom .config file is provided in u-boot-microblaze-howto/configs.

cd u-boot
cp ../u-boot-microblaze-howto/configs/.config .
make olddefconfig
make EXT_DTB="../dts/system.dtb" -j$(nproc)

Bundle u-boot SPL and bitstream

Create final bitstream which has the u-boot spl binary embedded inside the BRAM local memory.

cp spl/u-boot-spl spl/u-boot-spl.elf
updatemem -meminfo ../vivado_output/project.mmi -data spl/u-boot-spl.elf -bit ../vivado_output/project.bit -proc design_1_i/microblaze_0  -out ../vivado_output/final.bit -force
cd ..

Generate BOOT.BIN

build_boot_bin.sh script and Makefile logic are used to automate the generation of BOOT.BIN:

cd u-boot-microblaze-howto
make XSA_FILE="../vivado_output/project.xsa" BIT_FILE="../vivado_output/final.bit" UBOOT_FILE="../u-boot/u-boot.bin" UBOOT_LOADADDR="0x5000000"

The generated BOOT.BIN file is available in u-boot-microblaze-howto/output/BOOT.BIN

Load BOOT.BIN on sd-card and boot

Hook up the USB-Serial converter on the Rx/Tx pins defined in the constraints file and you should get to the u-boot console:

sudo screen /dev/ttyUSB0 9600

U-Boot SPL 2022.01-00846-g98a90b2730-dirty (Jan 30 2022 - 17:48:24 +0200)
SPL: Unsupported Boot Device!
Trying to boot from RAM

<debug_uart>


U-Boot 2022.01-00846-g98a90b2730-dirty (Jan 30 2022 - 19:04:26 +0200)

Model: Xilinx MicroBlaze
DRAM:  64 MiB   
Core:  4 devices, 3 uclasses, devicetree: embed
Loading Environment from nowhere... OK
In:    serial   
Out:   serial   
Err:   serial   
Net:   No ethernet found.
U-BOOT for

U-Boot-mONStR>

ovpanait / u-boot-microblaze-howto