openhwgroup / core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

Home Page:https://docs.openhwgroup.org/projects/core-v-verif/en/latest/index.html

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Generation of illegal instructions with corev-dv (riscv-dv)

MikeOpenHWGroup opened this issue · comments

In pull-request #2380 I commented that the function insert_illegal_instr() in cv32e40p/env/corev-dv/instr_lib/cv32e40p_float_instr_lib.sv does not actually create illegal instructions(!). I now understand why that is, but the next person to see this code will have the same question.

Please add a comment block explaining the rationale for this function and how corev-dv actually generates illegal instructions.

Solved in pull-request #2385.