Mike Thompson's repositories
cv32e40p-riscof
✔️Port of RISCOF to demonstrate the CV32E40P Processor's RISC-V ISA compatibility.
core-v-cores
CORE-V Family of RISC-V Cores
core-v-mcu-uvm
CORE-V MCU UVM Environment and Test Bench
core-v-xif
RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
siliconcompiler
SiliconCompiler is an open source compiler framework that automates translation from source code to silicon.
advanced-riscv-verification-methodologies
Advanced Verification Methodologies for RISC-V and related IP
bare-metal-programming-guide
A bare metal programming guide (ARM microcontrollers)
core-v-mcu
This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
core-v-mcu-cli-test
Eclipse/FreeRTOS/core-v-mcu example program
core-v-mcu-devkit
This is the CORE-V MCU DevKit project, hosting the open-source artifacts for the CORE-V MCU Development Kit.
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
cv32e40x-dv
CV32E40X Design-Verification environment
cve2
Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
cvw
Configurable RISC-V Processor
DVplan_reviewer
Experimenting with DVplan reviews
egos-2000
A minimal operating system (2K LOC) on QEMU and a RISC-V board
force-riscv
Instruction Set Generator initially contributed by Futurewei
programs
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
riscv-profiles
RISC-V Architecture Profiles
verilog-ethernet
Verilog Ethernet components for FPGA implementation
x-heep
eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V