openhwgroup / core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

Home Page:https://docs.openhwgroup.org/projects/core-v-verif/en/latest/index.html

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Replace uvma_axi_macros with non-random values in the cfg object

MikeOpenHWGroup opened this issue · comments

As of afb560d, there is a set of SystemVerilog macros in uvma_axi_macros that define a set of limits for various random members of uvma_axi5 agent. The use of SV macros for configuration should be avoided as they are global in scope and subect to change at compile-time.

These macros should be replace with non-random members of the cfg class.