openhwgroup / core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

Home Page:https://docs.openhwgroup.org/projects/core-v-verif/en/latest/index.html

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Clarify new illegal handler code for HWLOOPs

MikeOpenHWGroup opened this issue · comments

In pull-request #2280, the corev-dv function cv32e40p_asm_program_gen::gen_illegal_instr_handler(int hart) was substantially updated to add illegal handler code for HWLOOPs:

  • If the illegal exception happened within a hwloop.
  • If yes , check if the illegal was the last instruction of an hwloop with at least 1 more iteration left.
  • If yes, then set MEPC to first instruction of hwloop instead of just incrementing by 4.
    Else MEPC is just incremented by 4.

The code is fine, but difficult for a human to follow (because it is SystemVerilog code that emits RISC-V assembler) so it would be good to add a comment header to the function to include the above information.