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openhwgroup / core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

Home Page:https://docs.openhwgroup.org/projects/core-v-verif/en/latest/index.html

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Assertion failure not firing under VCS on CV32E20 simulations

MikeOpenHWGroup opened this issue · comments

commented

While reviewing pull-request #2240 it was discovered that a set of assertions that should be firing were not firing when simulating with VCS. See the PR for details. It is likely that the Makefiles for VCS has either disabled asserts or perhaps failed to enable them.