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olofk / serv

SERV - The SErial RISC-V CPU

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Simulation of the core itself?

YiminGao0113 opened this issue · comments

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Hi,

I wanted to ask if it's possible to simulate the SERV core using the provided software but without involving the System-on-Chip. I've been working on integrating SPI/I2C with the core and am looking for ways to verify my work. Could you give me any suggestions on how to proceed with this verification?

Thanks for your help! :)