SystemVerilog-project
Project for the class "Digital Low-level Hardware Systems II" in SystemVerilog.
This project implements an up/down counter, as well as a synchronous FIFO memory. The code includes the modules, property files and testbenches.
Project for the class "Digital Low-level Hardware Systems II" in SystemVerilog.
Project for the class "Digital Low-level Hardware Systems II" in SystemVerilog.
This project implements an up/down counter, as well as a synchronous FIFO memory. The code includes the modules, property files and testbenches.
Project for the class "Digital Low-level Hardware Systems II" in SystemVerilog.