Implementation of the paper of the same name for 'Digital VLSI Design' class. Done in a team of 3 with Shreya Gupta and NagaSunethra Vysyaraju
We implemented this paper and tried to optimize leakages for inverter and full adder while following delay constraints. The results will give W/L values for the circuit which yield optimal leakages. Hspice was used to calculate delays and leakages of a netlist.