myy1966

hashcat

World's fastest and most advanced password recovery utility

kkndme_tianya

天涯 kkndme 神贴聊房价

Open3D

Open3D: A Modern Library for 3D Data Processing

john

John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs

awesome-resume-for-chinese

:page_facing_up: 适合中文的简历模板收集（LaTeX，HTML/JS and so on）由 @hoochanlon 维护

openwifi

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

alien

ALIEN is a CUDA-powered artificial life simulation program.

glasgow

Scots Army Knife for electronics

neorv32

:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Silice

Silice is an easy-to-learn, powerful hardware description language, that simplifies designing hardware algorithms with parallelism and pipelines.

zipcpu

A small, light weight, RISC CPU soft core

cariboulite

CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR

hdmi

Send video/audio over HDMI on an FPGA

vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

uhd

The USRP™ Hardware Driver Repository

dsp-theory

Theory of digital signal processing (DSP): signals, filtration (IIR, FIR, CIC, MAF), transforms (FFT, DFT, Hilbert, Z-transform) etc.

luna

Amaranth HDL framework for monitoring, hacking, and developing USB devices

Fastor

A lightweight high performance tensor algebra framework for modern C++

nmigen

A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

cvfpu

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

RV12

RISC-V CPU Core

snitch

⛔ DEPRECATED ⛔ Lean but mean RISC-V system!

core-v-mcu

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

condensa

Programmable Neural Network Compression

MNSIM-2.0

A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems

fpga_image_processing

IP operations in verilog (simulation and implementation on ice40)

sdk

SIngle-Cycle-RISC-V-In-Verilog

This repository contains the verilog code files of Single Cycle RISC-V architecture

OSNASLib

OSNASLib is a general one-shot NAS framework empowering uses to incorporate one-shot NAS methods into various tasks (e.g. face recongition) easily.

RISCVSingleCycleProcessor

A RISC-V Single Cycle Processor which is done in verilog.