Mustafa Tosun's repositories
avst_adder
Example setup for UVM driven Icarus Verilog Simulation
dvb_fpga
RTL implementation of components for DVB-S2
medianSortBTNC
median sort project with verilog
OpenFPGA
An Open-source FPGA IP Generator
StdCellLib
LibreSilicon's Standard Cell Library Generator
UVVM
UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/
vsdflow
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.
vsdfpga
Implementation of Mixed Signal SoC (RISCV based Core + PLL) on Xilinx Artix-7 FPGA