mohamed

fsm2sv

SystemVerilog FSM generator

roofline

A simple script to plot the Roofline model for given HW platforms and applications

cordic

Synthesizable SystemVerilog implementation of fixed-point CORDIC algorithm

dotfiles

Backup of my dotfiles

field_ii_examples

Examples of the Field-II Ultrasound program

pysss

A Python implementation of Shamir's secret sharing algorithm

abc

ABC: System for Sequential Logic Synthesis and Formal Verification

bat.vim

Vim syntax highlighting based on the bat CLI tool

Learn-Vim

A book for learning the Vim editor

libcorrect

C library for Convolutional codes and Reed-Solomon

libriddle

A C library that implements Shamir secret sharing algorithm

LibToolingExample

An example of how to use Clang's LibTooling interface.

matmul

Various C++ implementations of matrix multiplication

mohamed.github.io

ninja

a small build system with a focus on speed

openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

OpenSTA

OpenSTA engine

pandoc_template

Pandoc Template for creating Trivadis CI like documentation.

reed-solomon

A demo of Reed-Solomon error correction

renode

Renode - Antmicro's virtual development framework for complex embedded systems

slang

SystemVerilog compiler and language services

sv2v

SystemVerilog to Verilog conversion

textbook

pysdr.org textbook source material, feel free to post issues/PRs

Tool-Solutions

Tutorials & examples for Arm software development tools.

unicorn

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)

vcml

A modeling library with virtual components for SystemC and TLM simulators

verible

Verible provides a SystemVerilog parser, style-linter, and formatter.

verilog-axi

Verilog AXI components for FPGA implementation

verilog-axis

Verilog AXI stream components for FPGA implementation

yosys

Yosys Open SYnthesis Suite