IC Design Project in Verilog for finding the maximum number in a sequence of 20 input numbers. Design stages:
- Writing the Verilog library of the basic gates;
- Writing the Verilog behavioral model of the circuit using the library of the basic gates;
- Functional testing of the behavioral model by the ModelSim;
- Synthesizing the behavioral model by the Yosys software and testing the synthesized model by the ModelSim;
- Writing the SDF file for the timing delays of the basic gates;
- Making a timing simulation of the whole circuit;
- Importing the circuit into the Electric VLSI and placing and routing the cells;
- Making a clock routing minimizing clock skew;
- Making an EDIFF file of the circuit.