mballance

clusterv-soc

Quad cluster of RISC-V cores with peripherals and local memory

bmk

Bare-Metal Kernel framework for embedded environments

caravel_fwpayload

Test project for the Open MPW shuttle

coremesh

SoC composed of 2d mesh of cores with chip-to-chip connectivity

mballance.github.io

Github Pages

PeakRDL-pss

PSS export generator for PeakRDL

simscripts

Basic simulation script and makefiles for executing simulation-based tests

ucoro

Experimental micro co-routine implementation for embedded systems

bitwuzla

Bitwuzla is a Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, floating-point arithmetic, arrays and uninterpreted functions and their combinations. Its name is derived from an Austrian dialect expression that can be translated as “someone who tinkers with bits”.

boolector

A Satisfiability Modulo Theories (SMT) solver for the theories of fixed-size bit-vectors, arrays and uninterpreted functions.

cadical_win32

CaDiCaL SAT Solver

caravel

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

caravel_fwpayload_dev

Standalone for fwpayload without the heavy-weight files

libboolector

Multi-platform super-build project for Boolector and dependent libraries

llm

Access large language models from the command-line

mpir

Multiple Precision Integers and Rationals

openpiton

The OpenPiton Platform

PeakRDL-uvm

Generate UVM register model from compiled SystemRDL input

py-tree-sitter-languages

Binary Python wheels for all tree sitter languages.

pygments

Pygments is a generic syntax highlighter written in Python

pygraphviz-bin

Python package embedding native binary builds of a stripped-down GraphViz

pyyaml-srcinfo-loader

Provides a custom loader for PyYAML that preserves source information about elements

rctgen

Rule-based concurrent test generator

riscv-dv

Random instruction generator for RISC-V processor verification

rouge

A pure Ruby code highlighter that is compatible with Pygments

templates

My collection of templates for use with VTE

tiny-soc

Example SoC using Featherweight IP blocks

tt-demo

verilator

Verilator open-source SystemVerilog simulator and lint system

zephyr

Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.