Beast code in Giters

Matthew Ballance's starred repositories

llm.c

LLM training in simple, raw C/CUDA

Language:CudaMIT23596 230 136

scalene

Scalene: a high-performance, high-precision CPU, GPU, and memory profiler for Python with AI-powered optimization proposals

Language:PythonApache-2.011615 87 467

ponyc

Pony is an open-source, actor-model, capabilities-secure, high performance programming language

Language:CBSD-2-Clause5686 141 1932

llm

Access large language models from the command-line

Language:PythonApache-2.04299 39 410

coz

Coz: Causal Profiling

Language:CNOASSERTION4053 70 142

d3-graphviz

Graphviz DOT rendering and animated transitions using D3

Language:JavaScriptBSD-3-Clause1683 32 184

BitNet

Implementation of "BitNet: Scaling 1-bit Transformers for Large Language Models" in pytorch

Language:PythonMIT1553 40 37

state-machine-cat

write beautiful state charts :scream_cat:

Language:TypeScriptMIT800 14 73

chisel-book

Digital Design with Chisel

Language:TeX745 36 18

pypyr

pypyr task-runner cli & api for automation pipelines. Automate anything by combining commands, different scripts in different languages & applications into one pipeline process.

Language:PythonApache-2.0589 15 138

basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

Language:SystemVerilogNOASSERTION503 30 183

pandoc-book-template

A simple Pandoc template to build documents and ebooks.

Language:CSSMIT390 12 15

pyuvm

The UVM written in Python

Language:PythonNOASSERTION362 31 52

profiles

site for discussing profiles design

CC-BY-4.0342 39 9

vscode-verilog-hdl-support

HDL support for VS Code

Language:TypeScriptMIT290 10 202

switchboard

Communication framework for RTL simulation and emulation.

Language:PythonApache-2.0255 7 56

scalehls

A scalable High-Level Synthesis framework on MLIR

Language:MLIRNOASSERTION217 15 61

filament

Fearless hardware design

Language:VerilogMIT141 7 186

PeakRDL

Control and status register code generator toolchain

Language:PythonGPL-3.091 13 35

ponylang-website

The ponylang.io website

Language:MarkdownBSD-2-Clause67 21 383

chimera

A tool for synthesizing Verilog programs

Language:VerilogGPL-3.029 3 22

eqy

Equivalence checking with Yosys

Language:PythonNOASSERTION29 8 25

cocotb-vivado

Limited python / cocotb interface to Xilinx/AMD Vivado simulator.

Language:PythonApache-2.028 70

timeline-chart

A timeline / gantt chart library for large data (e.g. traces)

Language:TypeScriptMIT27 17 66

hwtHls

LLVM based HLS library for HWToolkit (hardware devel. toolkit)

Language:PythonMIT25 4 1

CedarEDA.jl

Top level CedarEDA integration package

Language:JuliaNOASSERTION19 40

BSVTools

Language:PythonMIT17 5 4

DbgKaleidoscopeOrcJit

Add support for debugging JITed code to ORC JIT from LLVM Kaleidoscope example

Language:C++1300

rohd-wave-viewer

Language:DartBSD-3-Clause700

PSS

Blogs related to Portable Stimulus and Test Standard

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