mateuspinto / simplified-mips-pipeline

A synthesizable simplified MIPS written in System Verilog

systemverilog systemverilog-hdl mips hardware hardware-designs

simplified-mips-pipeline

A simplified mips with pipeline using my own verilog/system verilog boilerplate

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A synthesizable simplified MIPS written in System Verilog

systemverilog systemverilog-hdl mips hardware hardware-designs

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Language:SystemVerilog 95.2%Language:Python 4.8%