manavshah-28

-RiScKy-

Development of a RISC-V core in Verilog.

manavshah-28

8_Bit_CPU

Design an 8 bit CPU in Logisim from the ground up using logic gates.

blinky-de0-nano

FPGA_robo

Designed and developed a line following robot for E yantra robotics competetion

fsm_sequence_detector

manavshah-28.github.io

Ubuntu_Dual_Boot

Windows 11 and ubuntu dual booting procedure

universal_mem_reader