manavshah-28

scrape-google-scholar-py

Extract data from all Google Scholar pages from a single Python module. NOTE: I'm no longer maintaining this repo. Chrome driver/selectors might need and update.

ece748_projects

ECE748

NCSU ECE 748 - Advanced Verification with UVM

ECE745_ASICVerification

Final Testbench for LC3 Microcontroller

ECE745

ASIC Verification SystemVerilog

ECE745_FINAL

LC3-Verification

Repo for ECE745 LC3 Verification Project

ece745

Verifiying a Wishbone to I2C Multiple Bus Controller using SystemVerilog

System-Verilog

sby

SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

riscv-formal

RISC-V Formal Verification Framework

riscv-compliance

TEMPORARY FORK of the riscv-compliance repository

riscv-arch-test

riscv-tests

verilog-axi

Verilog AXI components for FPGA implementation

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

verilog-pcie

Verilog PCI express components

UVMReference

Reference examples and short projects using UVM Methodology

SystemVerilogReference

training labs and examples

I2SRV32-V-v1

Reconfigurable Computing Lab, DESE, Indian Institiute of Science

riscv-vector

Vector Acceleration IP core for RISC-V*

github-portfolio

Create a Portfolio Website using your GitHub username. This website template is constructed with next.js and tailwind CSS, allowing you to display your work and skills as a software developer.

RISC-V-vector-processor

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

ECE745_LC3_Verification

North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog

APD-OpenLANE-SkyWater130-Workshop

This Repository mainly created to focus on the work-done in 5 Days workshop of Adavance Physical Design using OpenLANE/SkyWater130. The Workshop mainly focus on to hands on experience of the efabless OpenLANE VLSI design flow RTL2GDS and the Skywater 130nm PDK. OpenLANE is an open source VLSI flow built around open source tools with the goal to produce clean GDSII with no human intervention. PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set .In this course this is used as an example to explain the flow .

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

OpenLANE-Sky130-Physical-Design-Workshop

Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130

OpenLANE-SkyWater130-workshop

This repository aims to capture the works done in 5-day workshop of Adavance Physical Design using OpenLANE/SkyWater130. The workshop helps to familiarise with the efabless OpenLANE VLSI design flow RTL2GDS and the Skywater 130nm PDK.

Convolutional-Neural-Network-hardware-using-Verilog

A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. This layer takes input from a memory. A MATLAB script was created to get the floating point inputs and convert it to 7 bit signed binary output. This was done for inputs as well as the weights in these two layers. Sigmoid case statement was also implemented in verilog to get the sigmoid values for intermediate outputs in a layer. This design was simulated and synthesized at 50 MHz on Quartus Prime 17.0. The FPGA family was Cyclone V. Total logic elements used were 724, total bits used 121856(only 50% use of memory).