manavshah-28 / -RiScKy-

Development of a RISC-V core in Verilog.

RV32I core design

• RV32I core design
  • Datapath
  • Supported Instructions (RV32I base instruction set)
  • Tech stack
  • Controller Design
  • Objectives
• Yosys
  • Using Yosys
    • diagram created by YOSYS

Datapath

Supported Instructions (RV32I base instruction set)

• add,sub,sll,slt,sltu,xor,srl,sra,or,and
• addi,slti,sltiu,xori,ori,andi,slli,srli,srai
• lb,lh,lw,lbu,lhu
• sb,sh,sw
• beq,bne,blt,bge,bltu,bgeu
• jal, jalr
• lui, auipc
• fence,ecall,ebreak

Tech stack

• Iverilog
• Gtkwave
• Verilog HDL
• Python
• Git/Github
• VS Code
• Yosys
• Graphviz

Controller Design

Objectives

• Study RV32I Instruction Set architecture.
• Design Datapth for single Cycle RV32I processor. (verilog).
• Design Controller.
• Design GUI for interfacing with data memory, registers and instruction hex files.
• Verify individual instructions with targeted assembly tests.
• understand verilator.
• understand makefiles.
• study other cores for grasping these concepts to move from verilog rtl to verification.
• Achieve complete RISCV compliance.

Yosys

• install yosys
• windows exe of yosys

Using Yosys

• press start in windows
• open command prompt
• go to the directory where your verilog files are stored
• <extracted_location>\oss-cad-suite\environment.bat
• This will open up OSS CAD Suite
• yosys
• This opens yosys
• 
• Now enter the command read_verilog RV32I.v
• 
• Next enter show RV32I
• 
• Install Graphviz
• Open another command prompt terminal and navigate to the same directory
• Enter the command dot -Tpng show.dot > output.png
• This will make a png image of your design with the name output.png

diagram created by YOSYS