m-kru's repositories
vhdl-simple
Library for simple VHDL entities
vhdl-examples
Examples of the VHDL syntax, libraries, packages, practices etc.
UVVM
UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/
vhdl-types
VHDL library collecting useful types that are frequently used, but are not part of the standard.
awesome-hdl
Hardware Description Languages
c-fixed-string
C module providing static strings (fixed sized). Useful for constraint systems without dynamic memory allocation.
c-log
Lightweight (single header file) C module implementing logging.
fbdl-example
FBDL Example
groff-utils
My groff files, memos, and scripts.
hbs
HBS (Hardware Build System) - the build system for hardware description projects.
kakoune
mawww's experiment for a better code editor
m-kru.github.io
Personal blog
vhdl-amba5
Library with VHDL cores implementing Advanced Microcontroller Bus Architecture 5 (AMBA5) specifications such as APB, AHB, and AXI.
vhdl-checkers
VHDL library containing checkers useful during simulation based verification.
vhdl-counters
VHDL library with various counters.
vhdl-format
VHDL String Formatting Library