pczarnecki's repositories
bazel-verilog-test
Testing verilog build rules from https://github.com/hdl/bazel_rules_hdl
yosys-f4pga-plugins
Plugins for Yosys developed as part of the F4PGA project.
buildx
Docker CLI plugin for extended build capabilities with BuildKit
vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
node_pcb
Kicad design - ESP32 node board
PolarPro3
QuickLogic device PolarPro3 Information
picofoxy
Pipelined In-order Core for Artix-7 Arty-35T board
litex
Build your hardware, easily!
CFU-Playground
Want a faster ML processor? Do it yourself! -- A framework for playing with using custom opcodes to accelerating TensorFlow Lite for Microcontroller (TFLM).
pythondata-cpu-vexriscv
Python module containing verilog files for vexriscv cpu (for use with LiteX).
sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
auto_pr_comments_from_forks
Shows how to make GitHub actions post PR comments from forked repositories
single_chan_pkt_fwd
Single Channel LoRaWAN Gateway
scripts
my utilities