lpawelcz

ar-translator

.cfg

.tmux

.vim

antlr_swing

auto_pr_comments_from_forks

Shows how to make GitHub actions post PR comments from forked repositories

bazel-verilog-test

Testing verilog build rules from https://github.com/hdl/bazel_rules_hdl

ble-gateway

ble-node-bme280

buildx

Docker CLI plugin for extended build capabilities with BuildKit

CFU-Playground

Want a faster ML processor? Do it yourself! -- A framework for playing with using custom opcodes to accelerating TensorFlow Lite for Microcontroller (TFLM).

comment-test

dl-picture-colorization

litex

Build your hardware, easily!

MIASI

miasi-eclipse

node_pcb

Kicad design - ESP32 node board

picofoxy

Pipelined In-order Core for Artix-7 Arty-35T board

PolarPro3

QuickLogic device PolarPro3 Information

ppiwd_server

python-netacad

pythondata-cpu-vexriscv

Python module containing verilog files for vexriscv cpu (for use with LiteX).

quicklogic-fasm

read-binary

scripts

my utilities

single_chan_pkt_fwd

Single Channel LoRaWAN Gateway

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

vim_my_plugins

vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.