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DiplomaticBackend

FPU

A chisel implementation of IEEE 754 mix-precision RISCV FPU

EPFL-StrongAuth-AutoFill

rocket-chip

Rocket Chip Generator

api-config-chipsalliance

A Scala library for Context-Dependent Evironments

berkeley-hardfloat

bsc

Bluespec Compiler (BSC)

chisel-testers2

Repository for chisel3 testers2 open alpha

chisel3

Chisel 3: A Modern Hardware Design Language

fpu-wrappers

Wrappers for open source FPU hardware implementations.

gcc-xs

GEM5Utils

HowToCook

程序员在家做饭方法指南。

map

Modeling Architectural Platform

memtester

Simple memory tester mirror from http://pyropus.ca/software/memtester/. Please note that I am not the author of Memtester

MIPSR10K

MIPS R10000 architecture simulator with C++

my-vim-config

NutShell

RISC-V SoC designed by students in UCAS

OrangeS

printf

Tiny, fast, non-dependent and fully loaded printf implementation for embedded systems. Extensive test suite passing.

pyverilator

Python wrapper for verilator model

RemoveCloneType

One line awk command for removing deprecated 'cloneType' since Chisel3.5.

riscv-binutils-gdb

RISC-V backports for binutils-gdb. Development is done upstream at the FSF.

riscv-gcc

riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC

rv8

RISC-V simulator for x86-64

verilator

Verilator open-source SystemVerilog simulator and lint system

XiangShan

Open-source high-performance RISC-V processor

ysyxSoC

zed

Code at the speed of thought – Zed is a high-performance, multiplayer code editor from the creators of Atom and Tree-sitter.