Top module: CHIP_All.sv testbench: Debug_tb_CHIP_All.sv
RTL simulation:
ncverilog Debug_tb_CHIP_All.sv +incdir+/opt/CAD/synopsys/synthesis/2019.12/dw/sim_ver/ -y /opt/CAD/synopsys/synthesis/2019.12/dw/sim_ver +libext+.v +notimingchecks +define+RTL +access+r
or just...
sh Debug.sh
sram generate list
| usage | # of sram | sram words | sram bits |
|---|---|---|---|
| Feature_based Method | |||
| 1 | line buffer for FAST | 6 | 640 |
| 4 | line buffer for BRIEF | 30 | 640 |
| 3 | FIFO for NMS | 1 | 640 |
| 2 | FIFO for sin, cos | 2 | 640 |
| 5 | desc in MATCH | 8 | 512 |
| 6 | desc in MATCH | 8 | 512 |
| 7 | point in MATCH | 1 | 512 |
| 8 | point in MATCH | 1 | 512 |
| 9 | depth in MATCH | 1 | 512 |
| 10 | depth in MATCH | 1 | 512 |
| ------------------------- | --------- | ---------- | --------- |
| Direct Method | |||
| line buffer for srcFrame | 1 | 640 | 24 |
| line buffer for dstFrame | 126 | 320 | 24 |
After integrated
| usage | # of sram | sram words | sram bits |
|---|---|---|---|
| Feature_based Method | |||
| desc in MATCH | 8 | 512 | 8 |
| desc in MATCH | 8 | 512 | 8 |
| ------------------------- | --------- | ---------- | --------- |
| Direct Method | |||
| line buffer for srcFrame | 1 | 640 | 24 |
| ------------------------- | --------- | ---------- | --------- |
| Shared | |||
| line buffer for dstFrame | 126 | 320 | 24 |