lirui-shanghaitech

A-convolution-kernel-implemented-by-Vivado-HLS

This project implements a convolution kernel based on vivado HLS on zcu104

Pintos-OS

Solution for Pintos assignment

A-multi-functions-digital-clock-based-on-8051

A multi-functions digital clock based on 8051, the corresponding proteus simulation circuit is also provided.

Cool-compiler

Solution to Cool compiler assignment

CS231n-solution

My solution to CS231n

ctoverilog

A C to verilog compiler

ecosoc

Automatically exported from code.google.com/p/ecosoc

learning-cmake

learning cmake

legup-dockerfile-1

legup-tmr

LegUpAsicImp

Master Thesis: High-Level synthesis for ASIC implementation using LegUp

libmem

Light-HLS

Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation.

LLVM-9.0-Learner-Tutorial

A blog for LLVM(v9.0.0 or v11.0.0) beginner, step by step, with detailed documents and comments. Record the way I learn LLVM and accomplish a complete project for FPGA High-Level Synthesis with it.

range-analysis

Static range analysis for the LLVM compiler infrastructure.

rbaa

Range Based Alias Analysis for LLVM

RELISH

Runahead Execution of Load Instructions via Sliced Hardware (RELISH) -- a High level synthesis optimisation pass, which automatically constructs helper circuits used to prefetch load instructions.

revsca

RevSCA-2.0

StitchUp

StitchUp is a plugin to the LegUp High Level Synthesis tool that enables the generation of fault tolerant FPGA circuits.

tclsh-wrapper

A tiny wrapper for Tcl/Tk's tclsh and wish

wfv

IMPORTANT NOTICE: This implementation is long outdated. The new libwfv will be released soon. Whole-Function Vectorization is an algorithm that transforms a scalar function in such a way that it computes W executions of the original code in parallel using SIMD instructions (W is the target architecture's SIMD width). This implementation of the algo

xronos

Xronos: High Level Synthesis of Streaming Applications