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lazar2222 / RISC-V-Debug

Implementation of RISC-V CPU with external debug support via JTAG

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debugrisc-vriscv-debug

Implementation of RISC-V CPU with external debug support

This repository hosts the source code, documentation, and materials for the Bachelor of Science thesis titled "Implementation of RISC-V CPU with External Debug Support" conducted at School of Electrical Engineering, University of Belgrade. Supervised by professor PhD Zaharije Radivojević, the project explores the development of a RISC-V CPU with external debug capabilities. For detailed information, please refer to:

Thesis
Presentation
Demo Video

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Implementation of RISC-V CPU with external debug support via JTAG

debugrisc-vriscv-debug

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