KinzaQamar

verification_training

verification training

common_peripheral_vips

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

openpiton

The OpenPiton Platform

Python4RTLVerification

SV-OOP-Examples

This repository contains the practice code related to SV OOP

basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

black-parrot

A Linux-capable RISC-V multicore for and by the world

black-parrot-sdk

black-parrot-sim

pwm-verification-IP

This repository contains the verification IP of PWM peripheral

riscv-aia

AIA IP compliant with the RISC-V AIA spec

2D-shapes-recognition

This repository contains the matlab code related to 2D image recognition

aia

C-practice

Cpp_practice

cs-video-courses

List of Computer Science courses with video lectures.

cv-hpdcache

RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores

git-practice

learn

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

PipelineC

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

pulpissimo

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

python-practice

riscv-aia-1

riscv-dv

Random instruction generator for RISC-V processor verification

riscvISACOV

SystemVerilog Functional Coverage for RISC-V ISA

serv

SERV - The SErial RISC-V CPU

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

SV-UVM-Examples

This repository contains the practice code related to SystemVerilog UVM

YAML-Practice