Kinza Qamar Zaman's repositories
basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
black-parrot
A Linux-capable RISC-V multicore for and by the world
pwm-verification-IP
This repository contains the verification IP of PWM peripheral
riscv-aia
AIA IP compliant with the RISC-V AIA spec
2D-shapes-recognition
This repository contains the matlab code related to 2D image recognition
bash_scripts
Journey of learning Bash
cs-video-courses
List of Computer Science courses with video lectures.
cv-hpdcache
RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
cvw
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
learn
Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.
muntjac
64-bit multicore RISC-V processor
opentitan
OpenTitan: Open source silicon root of trust
pequeno_riscv
Pequeno aka pqr5 is a pipelined in-order RISC-V CPU Core compliant with RV32I
PipelineC
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
pulpissimo
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
riscv-dv
Random instruction generator for RISC-V processor verification
riscvISACOV
SystemVerilog Functional Coverage for RISC-V ISA
serv
SERV - The SErial RISC-V CPU
tvip-axi
AMBA AXI VIP