Kien Le-Trung 's starred repositories
Ultra96V2_DPU_CityScapes
Deploy city objects sementic segmentation model in Xilinx FPGA ZU+
Ultra96v2-sandbox
Sandbox for Avnet's Ultra96v2 MPSoC Eval board
Xilinx-Vitis-AI
The Flow to Deploy your Custom Deep Learning Models on Ultra96V2.
DPU-PYNQ-Ultra96v2
This repository contains the procedures and files for NN model quantization and deployment with Vitis-AI on DPU-PYNQ for Ultra96v2.
TFModeltoEdge
repo for pretrained tf keras models and conversion to xilinx Ultra96v2 DPU
FPGA_accelerated_CNN
Accelerating a DCNN (VGG16) with an FPGA by implementing GEMM convolutional Kernel on AWS F1 FPGA and integrate into Pytorch using C++ extension
neural-network-fpga
Implementing LSTM recurrent neural network on FPGA board.
CNN-Based-FPGA
CNN implementation based FPGA
knn-fpga-hls
FPGA implementation of a handwritten digit recognition system based on k-nearest-neighbors (k-NN) classifier algorithm.
NN_Pattern_FPGA
Neural Network for Pattern Recognition on an FPGA. Project for Education. Video lectures explain training of the network and FPGA implementation with VHDL.
MobilenetOnZynq
Implemention of MobilenetV1 on FPGA
CNN-MobileNet-V1-implementation-on-AWS-FPGA-using-OpenCL
Increasing the accuracy of Convolutional Neural Networks (CNNs) has become a recent research focus in computer vision applications. Smaller CNN architectures like SqueezeNet and MobileNet can demonstrate accelerated performance on FPGAs and GPUs due to smaller model size and fewer network parameters. Implementation of CNNs on accelerators have two important benefits - GPUs provide thread-level parallelism to achieve higher throughput and FPGAs offer a customizable application-specific datapath. These two reasons make these platforms better suited for convolution like operations which involve huge data. This project aims to implement one such CNN architecture, MobileNet on an Image dataset in OpenCL, thereby comparing kernel execution time and memory bandwidth usage on FPGA and GPU
dnn-kernel-fpga
A project for self-implementation of deep learning on FPGAs
dcgan-fpga
Verilog implementation of the generator of DCGAN on FPGA
MobileNet-V2-inference-HLS
Codes to implement MobileNet V2 in a FPGA
Fpga-Implementation-of-Precise-Convolutional-Neural-Network-for-Extreme-Learning-Machine
Feed-forward neural networks can be trained based on a gradient-descent based backpropagation algorithm. But, these algorithms require more computation time. Extreme Learning Machines (ELM’s) are time-efficient, and they are less complicated than the conventional gradient-based algorithm. In previous years, an SRAM based convolutional neural network using a receptive – field Approach was proposed. This neural network was used as an encoder for the ELM algorithm and was implemented on FPGA. But, this neural network used an inaccurate 3-stage pipelined parallel adder. Hence, this neural network generates imprecise stimuli to the hidden layer neurons. This paper presents an implementation of precise convolutional neural network for encoding in the ELM algorithm based on the receptive - field approach at the hardware level. In the third stage of the pipelined parallel adder, instead of approximating the output by using one 2-input 15-bit adder, one 4-input 14-bit adder is used. Also, an additional weighted pixel array block is used. This weighted pixel array improves the accuracy of generating 128 weighted pixels. This neural network was simulated using ModelSim-Altera 10.1d and synthesized using Quartus II 13.0 sp1. This neural network is implemented on Cyclone V FPGA and used for pattern recognition applications. Although this design consumes slightly more hardware resources, this design is more accurate compared to previously existing encoders.
LeNet-on-Zynq
Simulating implement of LeNet network on Zynq-7020 FPGA
FPGA_random_forest
FPGA implementation of SKLearn Random Forest
Guide-to-FPGA-Implementation-of-Arithmetic-Functions
Examples from the book by Deschamps et al. https://www.amazon.com/Implementation-Arithmetic-Functions-Electrical-Engineering/dp/9400729863
cnn_hardware_acclerator_for_fpga
This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs