kgokarn

hammer

Hammer: Highly Agile Masks Made Effortlessly from RTL

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

htm.core

Actively developed Hierarchical Temporal Memory (HTM) community fork (continuation) of NuPIC. Implementation for C++ and Python

cuFHE

CUDA-accelerated Fully Homomorphic Encryption Library

eif

Extended Isolation Forest for Anomaly Detection

side-channel-analysis-toolbox

This is a project in which side-channel attacks are researched and developed.

falcon.py

A python implementation of the signature scheme Falcon

sat_atpg

SAT-based ATPG using TG-Pro model

Atalanta

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.

nerv

Naive Educational RISC-V -- A simple single-stage RV32I processor

edalize

An abstraction library for interfacing EDA tools

iverilog

Icarus Verilog

riscv-pk

RISC-V Proxy Kernel

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

NetA

RTL_INFOTRACK

The repo contains the binary to perform RTL information tracking for hardware Trojan and hardware vulnerabilities detection and tracking.

simple-riscv

A simple three-stage RISC-V CPU

jpeg_open

A hardware MJPEG encoder and RTP transmitter

cnn_open

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

jpeg_fpga

Implementation of JPEG Compression on an FPGA

jpeg_comp_verilog

JPEG Compression RTL implementation

jpeg-image-compression

This project has 2 parts. (1) JPEG image compression is been implemented into Matlab and (2) Verilog language using Xilinx software.

Kotlin-SDK

Kotlin-SDK for thenewboston.

linux

Linux kernel source tree

FreeRTOS-Kernel

FreeRTOS kernel files only, submoduled into https://github.com/FreeRTOS/FreeRTOS and various other repos.

Ciphey

⚡ Automatically decrypt encryptions without knowing the key or cipher, decode encodings, and crack hashes ⚡

libsystemctlm-soc

SystemC/TLM-2.0 Co-simulation framework

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

riscv-isa-sim

Spike, a RISC-V ISA Simulator

riscv-isa-manual

RISC-V Instruction Set Manual