Beast code in Giters

Joris Lee's starred repositories

leosoc-gfmpw-1

A simple dual-core SoC with true random number generators as payload.

Language:VerilogApache-2.0100

TRNG-with-Ring-Oscillators-in-Verilog

A true random number generator with ring oscillators structure written in VHDL targeting FPGA's.

Language:Verilog900

FPGA-based-True-Random-Number-Generator

True random number generators (TRNGs) play a fundamental role in cryptographic systems. This brief presents a new and efficient method to generate true random numbers on field programmable gate array (FPGA) by utilizing the random jitter of free-running oscillators as a source of randomness.

Language:Verilog200

COSO-TRNG

Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.

Language:VerilogMIT1000

gatemate_experiments

Experiments with Cologne Chip's GateMate FPGA architecture

Language:VHDLNOASSERTION1500

neoTRNG

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

Language:VHDLBSD-3-Clause15900

airisc_core_complex

Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.

Language:VerilogNOASSERTION7800

orp

Language:C41900

lwtrng

lightweight TRNG core for LiteX

Language:VerilogNOASSERTION1100

Rosebud

Framework for FPGA-accelerated Middlebox Development

Language:VerilogMIT3300

riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC

Language:CNOASSERTION326100

Cortex-M3-DesignStart-Eval

Cortex-M3 DesignStart Eval is intended for system Verilog design and simulation of a prototype SoC based on the Cortex-M3 processor.

MIT100

ARM_M3_design

personal practice

Language:Verilog900

Practical-Cryptography-for-Developers-Book

Practical Cryptography for Developers: Hashes, MAC, Key Derivation, DHKE, Symmetric and Asymmetric Ciphers, Public Key Cryptosystems, RSA, Elliptic Curves, ECC, secp256k1, ECDH, ECIES, Digital Signatures, ECDSA, EdDSA

Language:CSSMIT332400