Joris Lee's repositories
ci_ecp5_docker
ci esp5 fpga of docker.
ci_arm_gcc_docker
arm-none-eabi-gcc compilation environment docker
ci_git_deploy_docker
ci git deploy docker.
ci_ice40_docker
ice40 compilation environment docker.
ci_sphinx_docker
Sphinx compilation environment docker.
lede
Lean's LEDE source
litex
Build your hardware, easily!
oui
🐛 A framework used to develop Web interface for OpenWrt. Use Nginx + Vue3 + Lua.
picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
PurPle-Pi-R1
SDK for IDO-SBC2D06, base on SSD20X V30 SDK.
pythondata-cpu-vexriscv
Python module containing verilog files for vexriscv cpu (for use with LiteX).
pythondata-cpu-vexriscv_smp
Python module containing verilog files for VexRiscv SMP CPU (for use with LiteX).
Rosebud
Framework for FPGA-accelerated Middlebox Development
ticydb
TicyDB is local key-value data-store library in single header written in C.
verilog-ethernet
Verilog Ethernet components for FPGA implementation
VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
zynq-aes
AES hardware engine for Xilinx Zynq platform