Joris Lee's starred repositories
openFPGALoader
Universal utility for programming FPGA
free-programming-books
:books: Freely available programming books
hadbadge2019_fpgasoc
FPGA SoC code and application example for Hackaday Supercon 2019 badge
verilog-axis
Verilog AXI stream components for FPGA implementation
vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
ariane-ethernet
open-source Ethenet media access controller for Ariane on Genesys-2
vexriscv-test
Random testing and experiments with VexRisc-V
vexriscv_ocd_blog
Repo that shows how to use the VexRiscv with OpenOCD and semihosting.
riscv-formal
RISC-V Formal Verification Framework
SHA_SM3_SM4-Encryption-Algorithm
With basic SM3 & SM4 Encryption IP implemented with both Verilog and C , along with package for switching between SHA and SM3
Chinese-Translation-of-PCI-Express-Technology-
Chinese Translation on <PCI Express Technology Comprehensive Guide to Generations 1.x, 2.x and 3.0> by Mindshare Mindshare
FPGA-RMII-SMII
An FPGA-based MII to RMII & SMII converter to connect 100M ethernet PHY chip such as LAN8720 or KSZ8041TLI-S. 基于FPGA的MII转RMII和MII转SMII，用来连接LAN8720、KSZ8041TLI-S等百兆以太网PHY芯片。
PurPle-Pi-R1
SDK for IDO-SBC2D06, base on SSD20X V30 SDK.
PurPle-Pi-R1-Actions
Github Actions for PurPle Pi R1
ice40-stm32-sdram
Test code to talk from STM32 MCU over FSMC to SDRAM on ICE40 FPGA
riscv-code-samples
Repository containing example demonstrating use of RISC-V extensions or proposed extensions.
FPGA-SM3-HASH
Description of Chinese SM3 Hash algorithm with Verilog HDL