jnorrid

Joshua Norrid's starred repositories

Sortable

Reorderable drag-and-drop lists for modern browsers and touch devices. No jQuery or framework required.

Language:JavaScriptMIT29124 411 1779

bubbletea

A powerful little TUI framework 🏗

Language:GoMIT25583 118 274

openai-python

The official Python library for the OpenAI API

Language:PythonApache-2.021229 287 705

langflow

⛓️ Langflow is a visual framework for building multi-agent and RAG applications. It's open-source, Python-powered, fully customizable, model and vector store agnostic.

Language:JavaScriptMIT21153 179 968

unilm

Large-scale Self-supervised Pre-training Across Tasks, Languages, and Modalities

Language:PythonMIT19186 297 1336

nuklear

A single-header ANSI C gui library

Language:C13667 553 658

Nuklear

A single-header ANSI C immediate mode cross-platform GUI library

Language:C8881 126 397

mapscii

🗺 MapSCII is a Braille & ASCII world map renderer for your console - enter => telnet mapscii.me <= on Mac (brew install telnet) and Linux, connect with PuTTY on Windows

Language:JavaScriptMIT7626 106 69

A RWKV management and startup tool, full automation, only 8MB. And provides an interface compatible with the OpenAI API. RWKV is a large language model that is fully open source and available for commercial use.

Language:TypeScriptMIT4830 43 335

lcc

The lcc retargetable ANSI C compiler

Language:C1974 104 32

zarr-python

An implementation of chunked, compressed, N-dimensional arrays for Python.

Language:PythonMIT1407 43 763

hdmi

Send video/audio over HDMI on an FPGA

Language:SystemVerilogNOASSERTION1048 43 31

oterm

a text-based terminal client for Ollama

Language:PythonMIT859 10 57

nosqlbench

The open source, pluggable, nosql benchmarking suite.

Language:JavaApache-2.0164 15 609

vicuna

RISC-V Zve32x Vector Coprocessor

Language:AssemblyNOASSERTION150 6 98

tcpser

Fork of Jim Brain's tcpser program

Language:C137 28 21

Basic-SIMD-Processor-Verilog-Tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

Language:VerilogGPL-3.0112 6 3