This is a SystemVerilog implementation of the MIPS 5-stage pipeline described in "Digital Design and Computer Architecture" (2nd ed.) by David M. Harris and Sarah L. Harris (Morgan-Kaufmann, 2013).
Note: top-level module is in file top.sv.
Repository from Github https://github.comjnestor/mips_L_pipeline
This is a SystemVerilog implementation of the MIPS 5-stage pipeline described in "Digital Design and Computer Architecture" (2nd ed.) by David M. Harris and Sarah L. Harris (Morgan-Kaufmann, 2013).
Note: top-level module is in file top.sv.