jiru1997 / design-and-verification-of-MCDF-phase3

design-and-verification-of-MCDF-phase3

systemverilog design-verification uvm apb

design-and-verification-of-MCDF-phase3

design-and-verification-of-MCDF-phase3

phase3 of MCDF project.

updated all verification environment by using UVM

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design-and-verification-of-MCDF-phase3

systemverilog design-verification uvm apb

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Language:SystemVerilog 95.4%Language:Python 4.1%Language:Makefile 0.6%