Jimmy Situ's repositories
riscv-openocd
Fork of OpenOCD that has RISC-V support
rocket-chip
Rocket Chip Generator
chisel-template
A template project for beginning new Chisel work
chisel-testers
Provides various testers for chisel users
chisel-tutorial
chisel tutorial exercises and answers, Jimmy use this repository to learn chisel, Do not fork or use this repository for other use, fork the original one
financial-data
Financial Data for US/CN/HK/TW stock
fpga-shells
A fork of sifive/fpga-shells, add more supported board
freedom
Source files for SiFive's Freedom platforms
gfwlist2dnsmasq
A shell script which convert gfwlist into dnsmasq rules.
graphHub
Jimmy's Graph Hub for Website Sharing
insightmaker
Open-source central command for InsightMaker.com: System Dynamics, Differential Equations, and Agent Based Modeling in the web browser.
inteltool
Provides information about the Intel CPU/chipset hardware configuration
jmWxBot
Jimmy's Wechat Robot
jmZYNQ
Jimmy's ZYNQ system
mcpat
An integrated power, area, and timing modeling framework for multicore and manycore architectures
OpenDwarfs
The OpenDwarfs project provides a benchmark suite consisting of different computation/communication idioms, i.e., dwarfs, for state-of-art multicore and GPU systems. The first instantiation of the OpenDwarfs has been realized in OpenCL.
project-template
A template for building new projects/platforms using the Rocket Core
pyclewn
A Vim front-end to gdb
pymcpat
Python interface with mcpat
riscv-boom
Berkeley Out-of-Order Machine
riscv-cores-list
RISC-V Cores, SoC platforms and SoCs
riscv-formal-bench
A wrapper for riscv-formal(https://github.com/SymbioticEDA/riscv-formal)
sifive-blocks
Common RTL blocks used in SiFive's projects
uart2bus
A fork of UART to Bus on OpenCores