jimmysitu

msfinance

msfinance offers Pythonic way to download market data from morningstar.com

verilog-axi-formal

Formal verification for alexforencich/verilog-axi using SymbiYosys

verilog-sim-benchmarks

Verilog Simulator Benchmarks, a fork from verilator website

gem5-bench

A wrapper for simulation with gem5

FormalCourseExercise

Exercise of Formal Verification Courseware

jmRocket

Jimmy's Rocket Chip

api-v1-client-python

Blockchain Bitcoin Developer APIs - Python

ariane

Ariane is a 6-stage RISC-V CPU capable of booting Linux

Comet

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

gem5

Jimmy's gem5, forked from

GeST

GeST (Generating Stress-Tests) is a Genetic Algorithm framework for automatic hardware stress-test generation. Related scientific publication https://ieeexplore.ieee.org/document/8695639

jimmysitu

Config files for my GitHub profile.

jimmysitu.github.io

JM's website on github

jmACL2

JM's ACL2 playground

jmBenchmark

Jimmy's Benchmark

jmCool

Jimmy's Cool Compiler, for https://lagunita.stanford.edu/courses/Engineering/Compilers/Fall2014/info

jmRocket-SDK

SDK for jmRocket

jmStockAnalysis

Jimmy's stock analysis

likwid

Performance monitoring and benchmarking suite

More_Equal_Animals_Chinese_Edition

《更平等的动物》中文版

nZDC-Compiler

A LLVM-3.7 compiler with nZDC error detection transfromation

oh

Silicon proven Verilog library for IC and FPGA designers

pyParallelTest

Just a python3 parallel example

stx_cookbook

Altera Advanced Synthesis Cookbook 11.0

veriformal

This repository contains source code of VeriFormal simulator and translator.

verilog-axi

Verilog AXI components for FPGA implementation

verilog2smt

Example to transform verilog to smtlib2

vhdlformal

This repository stores the source code of a domain-specific language: a formalized version of VHDL embedded in Isabelle/HOL.

waveform-render-vscode

Render waveforms inside VSCode with WaveDrom