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jhmorris3486 / Rift2Core

Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.

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Rift2Core

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Based on Chisel3, Rift2Core is a 9-stage, dual-issue, out-of-order, 64-bits RISC-V Core, which supports RV64GC and M, S, U mode.

RiftCore is the previous version of Rift2Core in Verilog.

How to Setup

  • Setup Repo
  • Setup sbt
  • Setup verilator and gtkwave
  • Compile chisel3 to verilog
  • Compile Model of Rif2Chip
  • Test a single ISA with waveform
  • Test all ISA without waveform

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About

Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.

License:Apache License 2.0

Languages

Language:Scala 62.3%Language:Verilog 19.9%Language:C 9.5%Language:Makefile 2.9%Language:C++ 2.4%Language:Python 1.4%Language:Assembly 1.1%Language:Batchfile 0.3%Language:Shell 0.1%