jhmorris3486's repositories
chipyard
An Agile Chisel-Based SoC Design Framework
iso-profiles
This is a mirror repo of iso-profiles
livehd
Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
OpenFPGA
OpenFPGA
OpenLane
NOTE: The master branch is frozen for OpenMPW2. Please direct any PRs to the develop branch. :: OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
QGnomePlatform
QPlatformTheme for a better Qt application inclusion in GNOME
Rift2Core
Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
riscv-gnu-toolchain
GNU toolchain for RISC-V, including GCC
SOFA
SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
SYMPL-GP-GPU-Compute-Engines
Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in open-source Verilog RTL for IEEE754-2008 compliant, 32-bit single-precision floating-point accelerated applications.
yosys-examples
Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)