Giters
jdryg
/
tis100cpu
TIS-100 CPU in VHDL
Geek Repo:
Geek Repo
Github PK Tool:
Github PK Tool
Stargazers:
11
Watchers:
2
Issues:
7
Forks:
0
jdryg/tis100cpu Issues
Generic Instruction Memory entity
Closed
9 years ago
Remove port instructions
Updated
9 years ago
Comments count
2
Feature proposal: Node performance counters
Updated
9 years ago
Comments count
2
Observe correct limits on register values: -999 to 999
Updated
9 years ago
Comments count
1
Cycle-accurate design
Updated
9 years ago
Comments count
5
SWP in ALU
Closed
9 years ago
Comments count
1
Read after Write bug
Closed
9 years ago
Comments count
1