Generic Instruction Memory entity
jdryg opened this issue · comments
Make the Instruction Memory entity generic and pass the program from the testbench. This way it'll be possible to simulate 2 or more nodes simultaneously.
TIS-100 CPU in VHDL
jdryg opened this issue · comments
Make the Instruction Memory entity generic and pass the program from the testbench. This way it'll be possible to simulate 2 or more nodes simultaneously.