jameshanlon

netlist-paths

A library and command-line tool for querying a Verilog netlist.

prng-testing

Facilities for testing PRNGs against various statistical test suites

cheese

The CHEESE Project website

convolutional-neural-network

An implementation of a convolutional neural network

hex-processor

A processor and tooling for the hex processor architecture

PIC12F1572-pwm

A PIC12F1572 PWM example program.

riscv-processor

A C++ simulator and SystemVerilog implementation of the RISC-V R32IM architecture.

dotfiles

jameshanlon.github.io

My homepage.

awesome-hardware-tools

List of awesome open source hardware tools

boost_graph_example

Example program showing how to use aspects of boost::graph

boost_python_example

Boost::python example

netlist-paths-tests

A suite of tests for netlist-paths, using third-party Verilog designs

sire

An early sire compiler targeting the XMOS XS1 architecture

slang

SystemVerilog compiler and language services

surelog-tool-example

An example of building SureLog as library for a tool

energy-wiki

finances

Fetch personal finance data from Google Sheets and generate a set of summary HTML reports.

first-thermal

floating-point

hw

RTL, Cmodel, and testbench for NVDLA

random123

Tracking D. E. Research's Random123 Library

rgb-stacks

LED light boxes

rsd

RSD: RISC-V Out-of-Order Superscalar Processor

sire-reboot

slang-tool

uhdm-tool-example

verilator

Verilator open-source SystemVerilog simulator and lint system

verilator-2

A fork of Verilator for development

xcmp