jaemyungkim's repositories
AI-Chip
A list of ICs and IPs for AI, Machine Learning and Deep Learning.
awesome-fpga-list
A collection of some awesome public FPGA projects.
awesome-yolo-object-detection
🚀🚀🚀 A collection of some awesome public YOLO object detection series projects.
BJUT_Tutorials
Things to learn for new students in the Lab for AI chips and systems of BJTU .
CFU-Playground
Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.
CNN-Accelerator-VLSI
Convolutional accelerator kernel, target ASIC & FPGA
data-gradients
Computer Vision dataset analysis
dnn-engine
AXI-Stream Universal DNN Engine with Novel Dataflow enabling 70.7 Gops/mm2 on TSMC 65nm GP for 8-bit VGG16
DNN_HLS_Accelerator
This repository contains source code for CNN layers of ALexNet using Xilinx HLS Vivado.
EfficientPyTorch
A PyTorch Framework for Efficient Pruning and Quantization for specialized accelerators.
finn
Dataflow compiler for QNN inference on FPGAs
finn-hlslib
Vivado HLS library for FINN
HandyFigure
HandyFigure provides the sources file (ususally PPT files) for paper figures
LilNetX
Official PyTorch implementation of LilNetX: Lightweight Networks with EXtreme Model Compression and Structured Sparsification
micronet
micronet, a model compression and deploy lib. compression: 1、quantization: quantization-aware-training(QAT), High-Bit(>2b)(DoReFa/Quantization and Training of Neural Networks for Efficient Integer-Arithmetic-Only Inference)、Low-Bit(≤2b)/Ternary and Binary(TWN/BNN/XNOR-Net); post-training-quantization(PTQ), 8-bit(tensorrt); 2、 pruning: normal、regular and group convolutional channel pruning; 3、 group convolution structure; 4、batch-normalization fuse for quantization. deploy: tensorrt, fp32/fp16/int8(ptq-calibration)、op-adapt(upsample)、dynamic_shape
nanodet
⚡Super fast and lightweight anchor-free object detection model. 🔥Only 1.8MB and run 97FPS on cellphone🔥
Neural-Networks-on-Silicon
This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning and computer architecture.
nni
An open source AutoML toolkit for automate machine learning lifecycle, including feature engineering, neural architecture search, model compression and hyper-parameter tuning.
numerical-linear-algebra
Free online textbook of Jupyter notebooks for fast.ai Computational Linear Algebra course
openhls
PyTorch model to RTL flow for low latency inference
pp4fpgas
Parallel Programming for FPGAs -- An open-source high-level synthesis book
repo
ZedBoard FPGA based Convolutional Neural Network (CNN) accelerator
RepVGG
RepVGG: Making VGG-style ConvNets Great Again
Systolic-array-implementation-in-RTL-for-TPU
IC implementation of Systolic Array for TPU
Tiny-YOLO-LSQ
This is an implementation of YOLO using LSQ network quantization method.
Vitis-AI
Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.
yolov2_xilinx_fpga
A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard