imere / binary16-counter

vhdl 16-bit binary counter

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Design and implement a 16Bit binary counter. It is required to design three clock signals, such as 0.1S, 1S, and 3S. The count value is displayed on the digital tube. When the 16-bit counter is full, the counter is automatically cleared and restarts counting.

  1. 5 digital display
  2. LED counter prompts when the counter is full

设计并实现对一个16Bit的二进制计数器。要求自行设计0.1S、1S、3S等三个时钟信号,计数值在数码管上显示,当16位计数器计满计数器自动清零重新开始计数。

  1. 5位数码管显示
  2. 计数器记满后发光二极管LED提示

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vhdl 16-bit binary counter


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Language:VHDL 100.0%